Semiconductor circuits generally include different memory technologies for storing program code and data. Typically, read only memory (ROM) storage technologies have been employed to store program code and electrically erasable programmable ROM (EEPROM) storage technologies have been employed to store data. In order to reduce the required surface area and the overall complexity of semiconductor circuits, however, it is desirable to replace the ROM and EEPROM storage technologies with a single storage technology that is suitable for storing both program code and data.
Over time, the meaning of the term “EEPROM” has changed from the general meaning—electrically erasable programmable ROM—to a meaning that refers to a specific type of non-volatile memory. The specific type of memory is addressable in small, often byte-sized, segments and consists of cells that generally contain two transistors. One transistor has a floating gate to store data; the second transistor is for selection purposes and isolates the floating gate transistor from the rest of the memory and therefore isolates unrelated electrical stimuli that can alter or “disturb” the data contents on the floating gate. The term “Flash” memory refers to memory architectures in which large numbers of memory cells are simultaneously written to the same data state—in a “flash.” Strictly speaking, Flash memories may consist of cells that contain any number of transistors, but the more recent, popular meaning refers to cells that contain a single transistor. In the following description, “EEPROM” refers to byte-addressable memories consisting of two-transistor memory cells and “Flash” refers to memories consisting of single transistors, large numbers of which can be erased simultaneously.
Non-volatile floating gate memory cells, such as the split gate Flash cell from Silicon Storage Technology, Inc. (SSTI) of Sunnyvale, Calif., are attractive candidates for replacing both ROM and EEPROM, due to their small cell size, high reliability, low power requirements, fast erase, and built-in select transistor. While EEPROM storage technologies require two transistors for each memory cell, Flash storage technologies only require one transistor for each memory cell. Flash storage technologies can emulate ROM storage technologies quite easily. Emulating the ability of EEPROM storage technologies to rewrite small portions of the memory array, however, proves quite difficult, mainly due to disturb conditions and reduced endurance.
FIG. 1 illustrates a conventional array 100 of split gate Flash transistors, such as the transistor MN0. Each split gate transistor is in a programmed or charged to a high threshold state when electrons are trapped on the floating gate. The programmed state is reached by applying a high voltage, on the order of 10 volts, to the source line (SOURCE) of the transistor MN0, a select voltage, on the order of 1.5 volts, to the control gate (GATE) of the transistor MN0, and a constant current, on the order of 2 μA, to the drain line (often referred to as the bit line) (DRAIN) of the transistor MN0. Under the conditions of the programmed state, hot electrons are generated under the split gate region and swept onto the floating gate by the high field that has been coupled onto the floating gate. This programming condition is often referred to as “source side channel hot electron programming.”
The selected transistor in an array 100 of transistors is the transistor where the selected column intersects with the selected row line. As shown in FIG. 1, there are several unselected transistors that are subjected to one or more of the programming conditions but are not the target (selected) cell. These cells are subject to program disturb, in which the electrical stimuli that are applied to the selected transistor are also partly, and undesirably, applied to the unselected cells. If transistor MN0 is the target cell, transistor MN1 is subjected to program conditions on the source and drain but has an unselected row or gate. Transistor MN3 sees the program conditions on the row and source lines but has an unselected drain line. The unselected condition on any one of the three transistor nodes is enough to inhibit significant programming during a single cycle but some incremental amount of disturb is incurred during each programming cycle. A large number of program cycles and therefore a large number of disturb events may eventually lead to a memory failure.
The erased (low threshold) state of a split gate Flash transistor, such as the transistor MN0, is achieved by discharging the floating gate via tunneling. This is achieved by applying a high voltage to the row of the target cell, while the source and drain are grounded. Strong capacitive coupling between the floating gate and the source node maintains a low voltage on the floating gate. This produces a large electric field between the control gate and the floating gate and subsequently electron tunneling, from floating gate to control gate, can take place. If transistor MN0 is the target cell, transistor MN3 will also be erased, since it shares a common row and source.
The architecture shown in FIG. 1 has a single source line connecting multiple pairs of rows. Alternatively, other prior art architectures have a single source line connecting a single pair of rows. In this case, similar program disturb conditions exist to those described above, but the number of disturb events on any row can be reduced. The cells on one pair of rows are not exposed to a disturb voltage on the source line during the time that a different pair of rows is being programmed. Further improvements to disturb characteristics are obtained by performing an erase and programming all cells in the pair of rows, as described, for example, in U.S. Pat. No. 5,289,411). Nevertheless, a large number of cells (i.e., much greater than a single byte) share a source line and a significant number of disturb events can occur.
In addition to program disturb, prior art memory arrays utilizing Flash memory cells may have reduced effective endurance. In many applications, including smart cards, the number of bytes of new data to be written at any one time is small. Since the erase block in a Flash array is relatively large, many bytes in the same block do not need to change data but are nevertheless erased because all bytes contained in the same erase block must be erased simultaneously. Such bytes are first read then erased and re-written with the same data that was held previously. Thus, many bytes experience unnecessary erase and programming cycles that would not otherwise be required, if the erase block was small. The number of times that a single bit can be erased and programmed and still maintain its ability to store new data without errors is finite and is referred to as endurance. While the intrinsic endurance is a function of cell characteristics and is not appreciably affected by architecture, the unnecessary erase program cycles subtract from the total number of cycles available for useful data changes.
Furthermore, the relatively large size of the erase block increases the amount of time required to program new data, if the number of bytes that are actually changing is small. Since all bytes contained in the same erase block must be erased simultaneously, there may be bytes that do not change but need to be re-written. Unlike the erase operation, the number of bytes that can be programmed simultaneously is limited by the capability of circuits peripheral to the memory array. Since the number of bytes that are programmed simultaneously is limited, the large erase block increases the required time to program small amounts of data.
Many semiconductor circuits require the switching of high voltages. For example, non-volatile memory devices on such semiconductor circuits require voltages to erase and program the memory device that are significantly higher than the voltages needed for other device functions. For example, in one exemplary technology, voltages of 15 volts on the gate and 10 volts on the source are required for the erase and program modes, respectively. Gated diode breakdown is a well-known condition that can occur in a metal oxide semiconductor (MOS) transistor under certain conditions. The drain/source breakdown voltage (BVDSS) is the drain/source breakdown voltage with 0 volts applied to the gate of an n-channel transistor and depends on the transistor fabrication process. In one exemplary technology discussed herein, BVDSS is approximately 13 volts for both n-channel and p-channel transistors. Thus, to avoid gated diode breakdown, the voltage across the drain/source must remain below the breakdown voltage, BVDSS, if the gate voltage is grounded. As previously indicated, however, in many semiconductor circuits, voltages greater than the breakdown voltage are needed. For example, the erase and program operations for non-volatile memories on a secure integrated circuit require voltage levels of 15 and 10 volts, respectively, on the high voltage power supply, Vep. Thus, the 15 volts required on the gate of an exemplary non-volatile memory device during an erase mode is generally higher than the BVDSS of the high voltage transistors.
A number of techniques have been proposed for avoiding gated diode breakdown, such as placing an additional transistor in series with the existing transistor. The additional transistor is typically gated by Vdd, thus preventing the high voltage on the output from reaching the drain of the existing transistor and limiting the drain voltage on the existing transistor to a value below the breakdown voltage. While such techniques effectively prevent gated diode breakdown in the transistor, circuits including such gated diode breakdown protection techniques are typically only capable of switching between an output voltage of 0 volts and the high voltage level of 15 or 10 volts. For some applications, however, it is necessary, to switch between an output voltage of Vdd and the high voltage level of 15 or 10 volts, which is not possible with such cascoded transistor implementations. For a more detailed discussion of such gated diode breakdown protection techniques, see, for example, U.S. patent application Ser. No. 10/338,551, entitled “Method and Apparatus for Avoiding Gated Diode Breakdown in Transistor Circuits,” filed Jan. 8, 2003, assigned to the assignee of the present invention and incorporated by reference herein.
A need exists for an architecture and design that employ non-volatile floating gate Flash memory cells to emulate EEPROM functionality without incurring the program disturb issues discussed above. A further need exists for an architecture that minimizes memory overhead by dividing a memory array into small pages. Another further need exists for an architecture that reduces the number of unnecessary erase/program cycles and improves both effective endurance and effective program speed when only small amounts of data are changing. Yet another need exists for a protection circuit that prevents gated diode breakdown in N-channel transistors that have a high voltage across the drain/source of the transistor, and provides greater flexibility on the output voltages that may be obtained.